Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007)

Vienna, Austria
Monday September 10^th - Thursday 13^th, 2007

[CHES 07][PROGRAM][ACCEPTED PAPERS][CHES DINNER][REGISTRATION][ACCOMMODATIONS][TRANSPORTATION][VENUE & VISA]

Accepted Papers

• Obfuscation Does not Prevent from Transient Fault Analysis
     Christophe Clavier (Gemalto)
• High-Speed True Random Number Generation with Logic Gates Only
     Markus Dichtl and Jovan Golic (Siemens AG and Telecom Italia)
• Side Channel Cryptanalysis of a Prime Generation Algorithm from CHES 2006
     Christophe Clavier and Jean-Sébastien Coron (Gemalto, France and University of Luxembourg, Luxembourg)
• Masking and Dual-Rail Logic don't add up
     Patrick Schaumont and Kris Tiri (ECE Department Virginia Tech and Digital Enterprise Group Intel Corporation)
• Highly regular algorithms for scalar multiplication
     Marc Joye (Thomson)
• Arithmetic Operators for Pairing-Based Cryptography
     Jean-Luc Beuchat and Nicolas Brisebarre and Jérémie Detrey and Eiji Okamoto (University of Tsukuba and Université Monnet and École Normale Supérieure de Lyon)
• On the Power of Bitslice Implementation on Intel Core2 Processor
     Mitsuru Matsui and Junko Nakajima (Mitsubishi Electric)
• A First-Order DPA Attack Against AES with Unknown Input and Output
     Josh Jaffe (Cryptography Research, Inc.)
• An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
     Tetsuya Izu and Jun Kogure and Takeshi Shimoyama (Fujitsu)
• RFID Noisy Reader How to Prevent from Eavesdropping on the Communication?
     O. Savry and F. Pebay-Peroula and F. Dehmas and G. Robert and J. Reverdy (CEA LETI)
• FPGA Design for Verifying Self-Certified Signatures on Koblitz Curves
     Kimmo Järvinen and Juha Forsten and Jorma Skyttä (Helsinki University of Technology, Finland)
• How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation
     Daisuke Suzuki (Mitsubishi Electric Corporation)
• TEC-Tree: A Low Cost and Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
     Reouven Elbaz and David Champagne and Ruby B. Lee and Pierre Guillemin and Lionel Torres and Gilles Sassatelli (Princeton University and STMicroelectronics and University of Monpellier)
• Gaussian Mixture Models for Higher-Order Side Channel Analysis
     Kerstin Lemke-Rust and Christof Paar (Ruhr University Bochum, Germany)
• PRESENT: An Ultra-Lightweight Block Cipher
     A. Bogdanov and L.R. Knudsen and G. Leander and C. Paar and A. Poschmann and M.J.B. Robshaw and Y. Seurin and C. Vikkelsoe (Horst-Goertz-Institute for IT-Security, Ruhr University Bochum and Technical University Denmark and France Telecom R&D)
• MAME: A compression function proposal for RFID applications
     Hirotaka Yoshida and Dai Watanabe and Katsuyuki Okeya and Jun Kitahara and Hongjun Wu and Ozgul Kucuk and Bart Preneel (Hitachi Ltd and Katholieke Universiteit Leuven)
• AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
     Owen Harrison and John Waldron (Computer Architecture Group, Computer Science, Trinity College Dublin, Ireland)
• Differential Behavioral Analysis
     Pascal Manet and Bruno Robisson (CEA-LETI SESAM Laboratory)
• Side Channel Cryptanalysis of a Higher Order Masking
     Jean-Sebastien Coron and Emmanuel Prouff and Matthieu Rivain (University of Luxembourg and Oberthur Card Systems)
• FPGA Intrinsic PUFs and Their Use for IP Protection
     Jorge Guajardo and Sandeep Kumar and Geert-Jan Schrijen and Pim Tuyls (Philips Research Laboratories)
• Collision Attacks on Alpha-MAC and Other AES-based MACs
     Alex Biryukov and Andrey Bogdanov and Dmitry Khovratovich and Timo Kasper (University of Luxembourg, Luxembourg, and Ruhr-Universitäat Bochum, Germany)
• Multi-Gigabit GCM-AES Architecture Optimized for FPGAs
     Stefan Lemsitzer and Johannes Wolkerstorfer and Norbert Felber and Matthias Braendli (Institute for Applied Information Processing and Communications TU Graz and Integrated System Laboratory ETH)
• Power-Analysis Resistant AES Implementation with Instruction Set Extensions
     Stefan Tillich and Johann Groszschaedl (Graz University of Technology)
• RF-DNA: Radio-Frequency Certificates of Authenticity
     Darko Kirovski and Gerald DeJean (Microsoft Research)
• Simulation-Based Evaluation of Logic Styles to Counteract Side-Channel Attacks
     F. Mace, F.-X. Standaert, J.-J. Quisquater (UCL Crypto Group)
• Evaluation of the Masked Logic Style MDPL on a Prototype Chip
     Thomas Popp and Mario Kirschbaum and Thomas Zefferer and Stefan Mangard (Graz University of Technology)
• Power and EM Attacks on Passive 13.56 MHz RFID Devices
     Michael Hutter and Stefan Mangard and Martin Feldhofer (Graz University of Technology)
• Collision Search for Elliptic Curve Discrete Logarithm over GF(2m) with FPGA
     Guerric Meurice de Dormale and Philippe Bulens and Jean-Jacques Quisquater (UCL DICE / Crypto Group)
• Hardware-Assisted Realtime Attack on A5/2 without Precomputations
     Andrey Bogdanov and Thomas Eisenbarth and Andy Rupp (Ruhr University Bochum)
• Two New Techniques of Side-Channel Cryptanalysis
     Alex Biryukov and Dmitry Khovratovich (University of Luxembourg)
• DPA-Resistance Without Routing Constraints? A cautionary note about MDPL security
     Benedikt Gierlichs (K.U.Leuven, ESAT/SCD-COSIC)